1. Field of the Invention
This invention relates generally to an adder circuit, and more particularly to a BCD corrected serial adder for a serial processor.
2. Prior Art
Serial adders are employed for performing computations in serial processors. The information which is supplied to such adders is in the form of a binary word, with each word being formed of a plurality of bytes, each corresonding to a decimal digit. Each byte is formed of four bits in binary coded decimal (BCD) format. These adders operate on each bit of the same weight of two binary words at any given time, beginning with the least significant bit (LSB) of the least significant digit (LSD) and ending with the most significant bit (MSB) of the most significant digit (MSD), and generating a sum and a carry with each such operation until the two words are added together.
These adders are also capable of performing a subtraction operation by adding the minuend word to the 2's complement of the subtrahend. The sum which is produced as the result of that addition is equal to the remainder which would have been produced by subtracting the subtrahend word from the minuend word, with the exception that a carry is also produced if the result is greater than zero.
Whenever such an adder is performing an addition operation and the resultant sum of that operation for each digit or byte is greater than the decimal number 9, a correction must be made. Also, whenever such an adder is performing a subtraction operation and the resultant sum for each digit or byte is less than zero, a correction must be made. That is, when such an adder is operating in the subtraction mode, a byte carry which corresponds to the decimal number 16 signifies that the subtraction operation produced a remainder greater than zero.
One technique which has been employed in the past for performing such addition and subtraction operations utilizes two full adders, with a first one of those adders being employed for adding each bit of two words serially. The output of this first adder is supplied to a four bit shift register, such that each bit of the sum byte can be examined in the addition mode to determine if it corresponds to a decimal number greater than 9. In the subtraction mode, the absence of a carry during the addition of the most significant bits of the two bytes signifies that the remainder byte contained in the shift register is less than zero. A logic circuit is employed for recognizing these two conditions and for generating a correction signal in response thereto. Another logic circuit generates a byte corresponding to the decimal number 6 in the addition mode when the byte contained in the serial register corresponds to a decimal number greater than the decimal number 9, and generates a byte corresponding to the decimal number 10 in the subtraction mode when the byte contained in the serial register corresponds to a remainder less than zero. The byte contained in the serial register is then added to the byte generated by the second logic circuit in the second full adder.
It can be appreciated, that the above described technique for performing a BCD correction employs a feed forward arrangement in which the sum or remainder byte is first generated to determine if a correction is required and then a correction signal is generated and fed forward to a second full adder. Such a feed forward technique involves more delay than is desirable for performing certain operations associated with the BCD corrected adder circuit. Furthermore, such a technique requires the use of a second full adder and a flip flop for storing the carry output of that second adder in addition to that required for storing the carry output of the first full adder.
When such a BCD corrected adder circuit is employed in a serial processor, it is often possible that the entire subtrahend word is greater than the minuend work, such that the remainder word will be less than zero. Under such conditions, provision must be made for generating a borrow signal to be employed by a main control circuit associated therewith for performing an appropriate operation in accordance with the significance of that condition. For example, if the serial processor is performing a subtraction operation, such a borrow signal will be employed for displaying a negative sign in the display of the remainder and will cause the main control circuit to take the 2's compliment of the answer. If, however, the serial processor is performing a division operation by a series of subtractions the main control circuit must recognize this condition and shift either the minuend word or the subtrahend word with respect to one another so that the subtrahend word will appear to be less than the minuend word. Some of the BCD corrected adder circuits of the prior art which employ the above mentioned technique had no provision for generating such a borrow signal when the remainder word was less than zero. However, when such provision was made in such BCD corrected adder circuits, the borrow signal could not be generated in sufficient time for the main control circuit to act thereon immediately upon completion of the subtraction operation. Accordingly, such a serial processor employing the above described BCD corrected adder required one word time of idle before the required correction at the end of each word subtraction operation could be performed. It can be appreciated that such idle time is not desirable.
The above mentioned BCD corrected adder circuit also employes random logic which is not desirable for a number of reasons. For a complete discussion of the disadvantages of random logic as opposed to regular logic, reference is made to Pending Application for Patent, Ser. No. 584,637, filed June 6, 1975, of Richard B. Simone.
Another problem associated with the above mentioned BCD corrected adder is that it requires three separate timing signals for performing the BCD correction. The first of those timing signals is employed for detecting the presence of a byte which exceeds the decimal number 10 in the addition mode and for detecting the absence of a byte carry in the subtraction mode. That first timing signal is also employed for adding the 8 weight of the BCD number 10 to the uncorrected sum result in the subtraction mode of operation. The second timing signal is employed for adding the 4 weight of the BCD number 6 in the addition mode and the third timing signal is employed for adding the 2 weight of the BCD numbers 6 and 10 in the addition and subtraction modes, respectively.
Another BCD corrected adder circuit was recently developed which eliminated some of the problems of the above mentioned circuit, but created other problems. That circuit employs a look up technique in which each bit of a corrected sum byte is generated simultaneously without the addition of another byte thereto. More particularly, this circuit employs a programmable logic array (PLA) which examines each bit of a particular sum byte and generates the corrected sum byte with each bit thereof being generated simultaneously. This circuit, however, employed a synchronous PLA which would not permit the generation of a present carry and a correction signal simultaneously. As a result of this disadvantageous condition, it was not possible for this circuit to generate a borrow signal within the required time for the main control circuit to detect the required correction for the remainder word in the subtraction mode. More particularly, this circuit also required one word time of idle whenever such a borrow signal was generated. However, this circuit, because of the PLA employed therein, has all the advantages of the regular logic of such a PLA as discussed in the above mentioned application for patent. Furthermore, this circuit only required one timing signal for performing the BCD correction operation.
Accordingly, it can be appreciated that a need exists for a BCD corrected adder circuit which not only has all of the advantages of the above two mentioned circuits, but is capable of generating a borrow signal in sufficient time such that it may be employed by a main control circuit without requiring one word time of idle. In addition, such a BCD corrected adder circuit is needed which has a minimum number of components, thereby reducing the cost thereof.